RTL Design Engineer

Job Description

<p>About the job you're considering</p><p>Join a collaborative and innovative team as an RTL Design Engineer, where you'll contribute to cutting-edge ASIC development in a dynamic, multi-disciplinary environment. In this role, you'll design and maintain synthesizable RTL for SoC and subsystem components, working closely with architecture, verification, and physical design teams across global sites. You'll help ensure performance, power, and quality goals are met through simulation, debugging, and integration support, while contributing to technical discussions and emulation efforts.</p><p>Your role</p><ul><li>Design and maintain RTL for SoC and subsystem components using Verilog/SystemVerilog</li><li>Collaborate with architecture, design, and verification teams across multiple time zones</li><li>Support synthesis, timing closure, and power optimization efforts</li><li>Debug simulation failures and assist in post-silicon validation</li><li>Contribute to emulation activities and technical status meetings</li></ul><p>Your skills and experience</p><ul><li>Bachelor's or Master's degree in Electrical or Computer Engineering, with 5+ years of hands-on RTL design experience targeting advanced ASIC technologies.</li><li>Proficiency with ASIC design tools (Synopsys, Cadence), including lint, CDC, LEC, and gate-level simulations.</li><li>Strong scripting skills (Python, Perl, TCL, Bash) for automation and efficiency.</li><li>Solid understanding of SoC integration, bus protocols (AXI, AHB, AMBA), and networking/encryption standards.</li></ul>